Invention Grant
- Patent Title: Synchronizing a translation lookaside buffer with page tables
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Application No.: US15437369Application Date: 2017-02-20
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Publication No.: US09928180B2Publication Date: 2018-03-27
- Inventor: Vyacheslav Vladimirovich Malyugin , Boris Weissman , Ganesh Venkitachalam , Min Xu
- Applicant: VMware, Inc.
- Applicant Address: US CA Palo Alto
- Assignee: VMware, Inc.
- Current Assignee: VMware, Inc.
- Current Assignee Address: US CA Palo Alto
- Agency: Patterson & Sheridan, LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00 ; G06F13/28 ; G06F12/1027 ; G06F9/455 ; G06F12/0891 ; G06F12/1045 ; G06F12/1009

Abstract:
The translation lookaside buffer (TLB) of a processor is kept in synchronization with a guest page table by use of an indicator referred to as a “T” bit. The T bit of the NPT/EPT entries mapping the guest page table are set when a page walk is performed on the NPT/EPT. When modifications are made to pages mapped by NPT/EPT entries with their T bit set, changes to the TLB are made so that the TLB remains in synchronization with the guest page table. Accordingly, record/replay of virtual machines of virtualized computer systems may be performed reliably with no non-determinism introduced by stale TLBs that fall out of synchronization with the guest page table.
Public/Granted literature
- US20170228320A1 SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH PAGE TABLES Public/Granted day:2017-08-10
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