• Patent Title: Display, timing controller and column driver integrated circuit using clock embedded multi-level signaling
  • Application No.: US12066553
    Application Date: 2005-11-10
  • Publication No.: US09934712B2
    Publication Date: 2018-04-03
  • Inventor: Yong-Jae Lee
  • Applicant: Yong-Jae Lee
  • Applicant Address: KR Seoul
  • Assignee: ANAPASS INC.
  • Current Assignee: ANAPASS INC.
  • Current Assignee Address: KR Seoul
  • Agency: Paratus Law Group, PLLC
  • Priority: KR10-2005-0088619 20050923
  • International Application: PCT/KR2005/003678 WO 20051110
  • International Announcement: WO2007/035014 WO 20170329
  • Main IPC: G09G3/20
  • IPC: G09G3/20 G09G3/36
Display, timing controller and column driver integrated circuit using clock embedded multi-level signaling
Abstract:
The present invention relates to a display, a timing controller and a column driver IC, and more particularly to a display, timing controller and column driver integrated circuit using clock embedded multi-level signaling. The present invention provides a timing controller including a transmitter for transmitting a transmission signal wherein a transmission clock signal is embedded therein between a transmission data signal to have a signal magnitude different from that of the transmission data signal. The present invention also provides a column driver integrated circuit including a receiving unit for separating a clock signal from a received signal using a magnitude of the received signal, and for performing a sampling of a received data signal from the received signal using the separated clock signal.
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