- 专利标题: Write assist circuit for lowering a memory supply voltage and coupling a memory bit line
-
申请号: US15135133申请日: 2016-04-21
-
公开(公告)号: US09940994B2公开(公告)日: 2018-04-10
- 发明人: Yifei Zhang , Mark J. Winter
- 申请人: Avago Technologies General IP (Singapore) Pte. Ltd.
- 申请人地址: SG Singapore
- 专利权人: Avago Technologies General IP (Singapore) Pte. Ltd.
- 当前专利权人: Avago Technologies General IP (Singapore) Pte. Ltd.
- 当前专利权人地址: SG Singapore
- 代理机构: Foley & Lardner LLP
- 主分类号: G11C11/00
- IPC分类号: G11C11/00 ; G11C11/419 ; G11C5/14 ; G11C11/412
摘要:
A circuit and method performs a write assist for a memory cell (e.g., a static random access memory cell (SRAM)). The method includes providing a lower supply voltage signal to a voltage supply node of the memory cell using a capacitor. The lower supply voltage signal is lower in voltage level than a supply voltage signal. The method further includes lowering a common signal provided to a write driver using the capacitor.
公开/授权文献
信息查询