Invention Grant
- Patent Title: Multi-die integrated circuit device with capacitive overvoltage protection
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Application No.: US15245699Application Date: 2016-08-24
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Publication No.: US09941224B2Publication Date: 2018-04-10
- Inventor: Washington Lamar , Maxim Klebanov
- Applicant: Allegro MicroSystems, LLC
- Applicant Address: US MA Worcester
- Assignee: Allegro MicroSystems, LLC
- Current Assignee: Allegro MicroSystems, LLC
- Current Assignee Address: US MA Worcester
- Agency: Daly, Crowley, Mofford & Durkee, LLP
- Main IPC: H01L29/00
- IPC: H01L29/00 ; H01L23/60 ; H01L23/495 ; H01L23/31 ; H01L25/065 ; H01L21/48 ; H01L21/56 ; H01L25/00

Abstract:
An electronic device includes a package, a plurality of external leads extending outside the package, a first die within the package having one or more first contacts electrically coupled to at least a first one of the external leads, and a second die within the package having one or more second contacts electrically coupled to at least a second one of the external leads. A capacitive coupling may be positioned between the first and second die to allow electrostatic discharge (ESD) current to flow between the first die and the second die in response to an ESD event and to electrically isolate the first and second die from each other in the absence of the ESD event.
Public/Granted literature
- US20180061784A1 MULTI-DIE INTEGRATED CIRCUIT DEVICE WITH CAPACITIVE OVERVOLTAGE PROTECTION Public/Granted day:2018-03-01
Information query
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