Apparatus and methods are disclosed herein for reducing I/O latency when accessing data using a direct memory access (DMA) engine with a parser. A DMA descriptor indicating memory buffer location can be stored in cache. A DMA descriptor read command is generated and can include a prefetch command. A descriptor with the indicator can be communicated to the DMA engine in response to the read. A second parser can detect the descriptor communication, parse the descriptor, and can prefetch data from memory to cache while the descriptor is being communicated to the DMA engine and/or parsed by the DMA engine parser. When the DMA engine parses the descriptor, data can be accessed from cache rather than memory, to decrease latency.