According to one embodiment, a synchronous semiconductor device is disclosed According to this embodiment, the synchronous semiconductor device includes a pulse width detection circuit to provide detection information responsive to a plurality of delay amounts being different from one another and at least one of a high pulse width and a low pulse width of a first clock signal. The detection information representing relationships in size between each of the plurality of delay amounts and the at least one of the high pulse width and the low pulse width of the first clock signal. A delay line control circuit coupled to the pulse width detection circuit and the delay line. The delay line control circuit configured to change a delay amount of the delay line by a step size determined responsive, at least in part, to the detection information.