A processor includes a first encoder configured to encode a regular bin block including at least one regular bin, a second encoder configured to encode a bypass bin block including at least one bypass bin, and a parameter calculating module comprising parameter calculating circuitry configured to determine context information for encoding the regular bin block and to transmit the context information to the first encoder. The first encoder and the second encoder may process the regular bin block and the bypass bin block simultaneously and in parallel during at least part of a specific processing cycle.