Invention Grant
- Patent Title: Systems and methods for wafer-level loopback test
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Application No.: US14339224Application Date: 2014-07-23
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Publication No.: US09977078B2Publication Date: 2018-05-22
- Inventor: Alvin Leng Sun Loke , Thomas Clark Bryan , Reza Jalilizeinali , Tin Tin Wee , Stephen Robert Knol , LuVerne Ray Peterson
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Haynes and Boone, LLP (36340)
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G01R31/3177 ; G01R31/3185 ; G01R31/317

Abstract:
Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.
Public/Granted literature
- US20160025807A1 SYSTEMS AND METHODS FOR WAFER-LEVEL LOOPBACK TEST Public/Granted day:2016-01-28
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