A gate protection circuit includes: a clock signal generator to generate a plurality of gate clock signals; a gate driver to output gate signals based on the plurality of gate clock signals, the gate driver including a plurality of gate driving circuits cascaded to each other; and a monitoring line configured to transmit a feedback signal based on the plurality of gate clock signals via the plurality of gate driving circuits to the clock signal generator. The clock signal generator is to block generation of the plurality of gate clock signals in response to the feedback signal.