- 专利标题： Digital duty cycle correction for frequency multiplier
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申请号： US15153496申请日： 2016-05-12
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公开(公告)号： US09985618B2公开(公告)日： 2018-05-29
- 发明人: Dongmin Park , Jong Min Park , Lai Kan Leung
- 申请人： QUALCOMM Incorporated
- 申请人地址： US CA San Diego
- 专利权人： QUALCOMM Incorporated
- 当前专利权人： QUALCOMM Incorporated
- 当前专利权人地址： US CA San Diego
- 代理机构： Qualcomm Incorporated-Toler
- 主分类号： H03D3/24
- IPC分类号： H03D3/24 ; H03K5/156 ; H03L7/081 ; H03L7/089 ; H03L7/091 ; H03L7/093 ; H03L7/16 ; H04L7/00 ; H04L7/033
摘要：
An apparatus includes a phase detector coupled to an output of a frequency multiplier. A digital loop filter is coupled to the phase detector, and a duty cycle correction circuit is coupled to the digital loop filter.
公开/授权文献
- US20170187364A1 DIGITAL DUTY CYCLE CORRECTION FOR FREQUENCY MULTIPLIER 公开/授权日：2017-06-29
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