A display device includes a timing controller configured to receive an image data signal and a plurality of clock signals and to generate a scan clock signal and a plurality of data clock signals, a scan driver configured to receive the scan clock signal, and a data driver configured to receive the data clock signals. The clock signals include first to nth clock signals, and the data clock signals include first to nth data clock signals generated from the first to nth clock signals (n≥2), the first to nth clock signals having differing frequencies and the first to nth data clock signals having differing frequencies. Whenever a predetermined number of frame periods has elapsed, the timing controller halts transmission of one of the first to nth data clock signals to the data driver, and begins transmission of another one of the first to nth data clock signals thereto.