Invention Grant
- Patent Title: Semiconductor assembly and method of manufacture
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Application No.: US13950736Application Date: 2013-07-25
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Publication No.: US09997507B2Publication Date: 2018-06-12
- Inventor: Avinash Srikrishnan Kashyap , Peter Micah Sandvik , Rui Zhou , Peter Almern Losee
- Applicant: General Electric Company
- Applicant Address: unknown Schenectady
- Assignee: General Electric Company
- Current Assignee: General Electric Company
- Current Assignee Address: unknown Schenectady
- Agency: Global Patent Operation
- Agent John P. Darling
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L21/8252 ; H01L21/8258 ; H01L27/02

Abstract:
A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.
Public/Granted literature
- US20150028469A1 SEMICONDUCTOR ASSEMBLY AND METHOD OF MANUFACTURE Public/Granted day:2015-01-29
Information query
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