再颁专利
- 专利标题： Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
- 专利标题（中）： 通用处理器架构中的能量和性能的内存层次结构重构
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申请号： US11645329申请日： 2006-12-21
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公开(公告)号： USRE41958E1公开(公告)日： 2010-11-23
- 发明人: Sandhya Dwarkadas , Rajeev Balasubramonian , Alper Buyuktosunoglu , David H. Albonesi
- 申请人： Sandhya Dwarkadas , Rajeev Balasubramonian , Alper Buyuktosunoglu , David H. Albonesi
- 代理机构： Stolowitz Ford Cowger LLP
- 主分类号： G11F12/08
- IPC分类号： G11F12/08 ; G11C15/00
摘要：
A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.
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