再颁专利
USRE43235E1 Single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generator
有权
单块虚拟帧缓冲区转换为多块物理块,用于多块显示刷新生成器
- 专利标题: Single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generator
- 专利标题(中): 单块虚拟帧缓冲区转换为多块物理块,用于多块显示刷新生成器
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申请号: US12789856申请日: 2010-05-28
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公开(公告)号: USRE43235E1公开(公告)日: 2012-03-13
- 发明人: Takatoshi Ishii , Edmund Cheung , Sherwood Brannon
- 申请人: Takatoshi Ishii , Edmund Cheung , Sherwood Brannon
- 申请人地址: US NV Las Vegas
- 专利权人: Faust Communications, LLC
- 当前专利权人: Faust Communications, LLC
- 当前专利权人地址: US NV Las Vegas
- 主分类号: G06F12/10
- IPC分类号: G06F12/10 ; G06F12/06 ; G09G3/37 ; G09G5/00 ; G09G5/36
摘要:
A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data, .eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.