再颁专利
- 专利标题: Bump-on-lead flip chip interconnection
- 专利标题(中): Bump-on-lead倒装芯片互连
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申请号: US13556106申请日: 2012-07-23
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公开(公告)号: USRE44431E1公开(公告)日: 2013-08-13
- 发明人: Rajendra D. Pendse
- 申请人: Rajendra D. Pendse
- 申请人地址: SG Singapore
- 专利权人: STATS ChipPAC, Ltd.
- 当前专利权人: STATS ChipPAC, Ltd.
- 当前专利权人地址: SG Singapore
- 代理机构: Patent Law Group: Atkins & Associates, P.C.
- 代理商 Robert D. Atkins
- 主分类号: H01L23/48
- IPC分类号: H01L23/48 ; H01L21/44
摘要:
A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. The fusible portion melts at a temperature which avoids damage to the substrate during reflow. The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.