A method for fabricating at least one via or hole in a multi-layer printed circuit board comprises separately drilling the board layers (3A, 3B, 3C) stacking and laminating the drilled board layers, and then finish drilling the holes (7A, 7B, 7C). The invention also provides a method for correcting artwork to compensate for lamination distortion. Also described is a process for forming interconnection lines on a printed circuit board. The surface of a circuit board substrate (105) is covered with a photoresist layer (107), and the photoresist layer in turn is covered with a halide emulsion layer (109). The emulsion layer (109) is then exposed to a predetermined pattern of white light, and the image developed. The board is then exposed to UV light through the imaged emulsion layer.