Invention Application
WO1994023448A1 PACKAGE FOR SEMICONDUCTOR CHIP 审中-公开
半导体芯片封装

PACKAGE FOR SEMICONDUCTOR CHIP
Abstract:
A package for a semiconductor chip having the following features: (a) a power-supply layer, a ground layer, and a signal layer are formed in multilayer through intermediate layers including insulating layers; (b) the power-supply layer and ground layer each comprise an inner lead region exposed from the intermediate layers, an outer lead region, and a conductive region sandwiched by these two regions and covered by the intermediate layers; and (c) the conductive regions of the power-supply layer and ground layer consist of planar conductive members. The self-inductances of the power-supply and ground layers of this package are low, and the capacitance of the capacitor formed by these layers is low. Therefore, the noise of the power-supply system is little.
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