A frame buffer (17) designed to be coupled to a data bus (12) and to an output display (18) in a computer system (Figure 1), the frame buffer (Frame 3) including an array of memory cells (52) for storing data indicating pixels to be displayed on the output display, address decoding apparatus (54 and 56) for controlling access to the array, the address decoding apparatus including column address decoding apparatus (56) for selecting groups of adjacent columns of the array, a plurality of apparatus for selectively writing to each of the columns of any of said groups of adjacent columns, a plurality of color value registers (C0 and C1), latching apparatus (57) for storing pixel data equivalent to a row of pixel data to be displayed on the output display, apparatus for writing pixel data from selected groups of adjacent columns of the array to the latching apparatus, and apparatus (58) for connecting either selected ones of the color value registers, the latches, or the data bus to the apparatus for selectively writing to each of the columns of any of said groups of adjacent columns.