Invention Application
WO0114971A9 SYSTEM AND METHOD FOR DETECTING DOUBLE-BIT ERRORS AND FOR CORRECTING ERRORS DUE TO COMPONENT FAILURES
审中-公开
用于检测双位错误和用于纠正由于组件故障而导致的错误的系统和方法
- Patent Title: SYSTEM AND METHOD FOR DETECTING DOUBLE-BIT ERRORS AND FOR CORRECTING ERRORS DUE TO COMPONENT FAILURES
- Patent Title (中): 用于检测双位错误和用于纠正由于组件故障而导致的错误的系统和方法
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Application No.: PCT/US0020960Application Date: 2000-08-01
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Publication No.: WO0114971A9Publication Date: 2001-11-01
- Inventor: CYPHER ROBERT
- Applicant: SUN MICROSYSTEMS INC
- Assignee: SUN MICROSYSTEMS INC
- Current Assignee: SUN MICROSYSTEMS INC
- Priority: US36820999 1999-08-04
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H03M13/09 ; H03M13/19
Abstract:
A system for detecting and correcting errors in a data block includes a check bits generation unit which receives and encode data to be protected. The check bits generation unit partition the data into a plurality of logical groups. The check bits generation unit generates a parity bit for each of the logical group and additionally generates a pair of global error correction codes. The error correction unit is configured to generate a parity error bit for each of the logical group of data based on the received data and the original parity bits, as well as first and second syndrome codes.
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