Invention Application
WO01088692A2 ACCELERATED MONTGOMERY MULTIPLICATION USING PLURAL MULTIPLIERS 审中-公开
使用多重乘法器的加速单体多项式

  • Patent Title: ACCELERATED MONTGOMERY MULTIPLICATION USING PLURAL MULTIPLIERS
  • Patent Title (中): 使用多重乘法器的加速单体多项式
  • Application No.: PCT/US2001/014616
    Application Date: 2001-05-07
  • Publication No.: WO01088692A2
    Publication Date: 2001-11-22
  • Main IPC: G06F1/00
  • IPC: G06F1/00 G06F7/72 G06F9/38 G06F21/00 G06F7/52
ACCELERATED MONTGOMERY MULTIPLICATION USING PLURAL MULTIPLIERS
Abstract:
Montgomery multipliers and methods modular multiply a residue multiplicand by a residue multiplier to obtain a residue product, using a scalar multiplier, a first vector multiplier and a second vector multiplier. A controller is configured to control the scalar multiplier, the first vector multiplier and the second vector multiplier, to overlap scalar multiplies using a selected digit of the multiplier and vector multiplies using a modulus and the multiplicand. The scalar multiplier is configured to multiply a least significant digit of the multiplicand by a first selected digit of the multiplier, to produce a scalar multiplier output. The first vector multiplier is configured to multiply the scalar multiplier output by a modulus, to produce a first vector multiplier output. The second vector multiplier is configured to multiply a second selected digit of the multiplier by the multiplicand, to produce a second vector multiplier output. An accumulator is configured to add the first vector multiplier output, and the second vector multiplier output, to produce a product output. The latency of Montgomery multiplication thereby can be reduced to nearly the latency of a single scalar multiplication.
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