The invention relates to a method and a device for adapting the clock-pulse rates of a first digital signal (DS1) which is inserted into pulse frames to a second clock-pulse rate (T2). The first signal (DS1) is continuously written into an intermediate memory (PS1) wherein several bits or bit sequences are stored intermediately. The first signal (DS1) is read out of the intermediate memory (PS1) with a second clock-pulse rate.A specific number of selected bits or bit sequences (BA) is inserted into the pulse frame during read-out or removed therefrom, whereby a second signal (DS2) is obtained with the desired second clock-pulse rate (T2), the number of bits or bit sequences being modified and the pulse frame being essentially of the same duration.