Invention Application
- Patent Title: COORDINATING IDLE STATE TRANSITIONS IN MULTI-CORE PROCESSORS
- Patent Title (中): 协调多核处理器中的空闲状态转换
-
Application No.: PCT/US2005/028699Application Date: 2005-08-12
-
Publication No.: WO2006028652A2Publication Date: 2006-03-16
- Inventor: NAVEH, Alon , MENDELSON, Avi , ANATI, Ittai , WEISSMANN, Eliezer
- Applicant: INTEL CORPORATION , NAVEH, Alon , MENDELSON, Avi , ANATI, Ittai , WEISSMANN, Eliezer
- Applicant Address: 2200 Mission College Boulevard, Santa Clara, CA 95052 US
- Assignee: INTEL CORPORATION,NAVEH, Alon,MENDELSON, Avi,ANATI, Ittai,WEISSMANN, Eliezer
- Current Assignee: INTEL CORPORATION,NAVEH, Alon,MENDELSON, Avi,ANATI, Ittai,WEISSMANN, Eliezer
- Current Assignee Address: 2200 Mission College Boulevard, Santa Clara, CA 95052 US
- Agency: VINCENT, Lester, J.
- Priority: US10/934,034 20040903
- Main IPC: G06F1/32
- IPC: G06F1/32
Abstract:
Systems and methods of managing processors provide for detecting a command at a core of a processor having a plurality of cores, where the command requests a transition of the core to an idle state. Power consumption of the core is managed based on the command and an idle state status of each of the plurality of cores.
Information query
