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Invention Application
WO2006132804A3 SYSTEM AND METHOD FOR POWER SAVING IN PIPELINED MICROPROCESSORS 审中-公开
在管道微处理器中节电的系统和方法

SYSTEM AND METHOD FOR POWER SAVING IN PIPELINED MICROPROCESSORS
Abstract:
A system and method for preserving power in a microprocessor pipeline (300). The system includes a register file read control unit (305), the read control unit (305) being configured to monitor one or more outputs from a control /decode unit (205) of the pipeline (300) and monitor write addresses from one or more other stages of the pipeline. The system also includes one or more read inhibit units (301, 303) each having an input, an output, and an enable terminal, the output of each of the one or more read inhibit units (301, 303) being coupled to a unique register port of a register file (109) within the pipeline (300). The input of each of the one or more read inhibit units (301, 303) being coupled to the control/decode unit (205), and the enable terminal of each of the one or more read inhibit units (301, 303) being coupled to a unique output of the read control unit (305).
Abstract(Chinese):

一种用于在微处理器管线（300）中保持功率的系统和方法。 所述系统包括寄存器文件读取控制单元（305），所述读取控制单元（305）被配置为监视来自所述流水线（300）的控制/解码单元（205）的一个或多个输出，并监视来自一个或 更多的其他阶段的管道。 该系统还包括一个或多个每个具有输入，输出和使能端的读取禁止单元（301,303），一个或多个读取禁止单元（301,303）中的每一个的输出被耦合到唯一的 管道（300）内的寄存器文件（109）的注册端口。 一个或多个禁止读取单元（301,303）中的每一个的输入被耦合到控制/解码单元（205），并且一个或多个禁止读取单元（301,303）中的每一个的使能端被耦合 到读取控制单元（305）的唯一输出。

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