Invention Application
- Patent Title: COORDINATING ACCESS TO MEMORY LOCATIONS FOR HARDWARE TRANSACTIONAL MEMORY TRANSACTIONS AND SOFTWARE TRANSACTIONAL MEMORY TRANSACTIONS
- Patent Title (中): 协调对硬件交易记录交易和软件交易记录交易的存储位置访问
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Application No.: PCT/US2006046499Application Date: 2006-12-05
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Publication No.: WO2007078538A3Publication Date: 2007-08-30
- Inventor: ADL-TABATABAI ALI-REZA , SAHA BRATIN , HUDSON RICHARD L , AKKARY HAITHAM , RAJWAR RAVI
- Applicant: INTEL CORP , ADL-TABATABAI ALI-REZA , SAHA BRATIN , HUDSON RICHARD L , AKKARY HAITHAM , RAJWAR RAVI
- Assignee: INTEL CORP,ADL-TABATABAI ALI-REZA,SAHA BRATIN,HUDSON RICHARD L,AKKARY HAITHAM,RAJWAR RAVI
- Current Assignee: INTEL CORP,ADL-TABATABAI ALI-REZA,SAHA BRATIN,HUDSON RICHARD L,AKKARY HAITHAM,RAJWAR RAVI
- Priority: US30352905 2005-12-15
- Main IPC: G06F9/52
- IPC: G06F9/52
Abstract:
Provided is a method, system, and program for coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions. A hardware transaction executing in hardware transactional memory initiates a request to access a memory location. A fault is returned to the hardware transaction request in response to an operation by one software transaction executing in a software transactional memory.
Information query
