Invention Application
- Patent Title: TWO-LEVEL INTERRUPT SERVICE ROUTINE
- Patent Title (中): 两级中断服务程序
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Application No.: PCT/US2007/062768Application Date: 2007-02-23
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Publication No.: WO2007101139A1Publication Date: 2007-09-07
- Inventor: BIRENBACH, Michael Egnoah , BROOKSHIRE, Gregory Lee , DIEFFENDERFER, James Norris , GEIST, Stephen, G. , MOORE, Richard Alan , SARTORIUS, Thomas Andrew , SMITH, Rodney Wayne
- Applicant: QUALCOMM INCORPORATED , BIRENBACH, Michael Egnoah , BROOKSHIRE, Gregory Lee , DIEFFENDERFER, James Norris , GEIST, Stephen, G. , MOORE, Richard Alan , SARTORIUS, Thomas Andrew , SMITH, Rodney Wayne
- Applicant Address: International IP Administration, 5775 Morehouse Drive, San Diego, California 92121 US
- Assignee: QUALCOMM INCORPORATED,BIRENBACH, Michael Egnoah,BROOKSHIRE, Gregory Lee,DIEFFENDERFER, James Norris,GEIST, Stephen, G.,MOORE, Richard Alan,SARTORIUS, Thomas Andrew,SMITH, Rodney Wayne
- Current Assignee: QUALCOMM INCORPORATED,BIRENBACH, Michael Egnoah,BROOKSHIRE, Gregory Lee,DIEFFENDERFER, James Norris,GEIST, Stephen, G.,MOORE, Richard Alan,SARTORIUS, Thomas Andrew,SMITH, Rodney Wayne
- Current Assignee Address: International IP Administration, 5775 Morehouse Drive, San Diego, California 92121 US
- Agency: OGROD, Gregory, D.
- Priority: US11/361,402 20060224
- Main IPC: G06F9/48
- IPC: G06F9/48
Abstract:
A processor provides two-level interrupt servicing. In one embodiment, the processor comprises a storage device and an interrupt handler. The storage device is configured to store an interrupt identifier corresponding to an interrupt request. The interrupt handler is configured to recognize the interrupt request, initiate a common interrupt service routine responsive to recognizing the interrupt request and subsequently initiate an interrupt service routine corresponding to the stored interrupt identifier.
Information query
