Invention Application
WO2007109326A2 METHODS AND MATERIALS USEFUL FOR CHIP STACKING, CHIP AND WAFER BONDING
审中-公开
用于芯片堆叠，芯片和波形结合的方法和材料
- Patent Title: METHODS AND MATERIALS USEFUL FOR CHIP STACKING, CHIP AND WAFER BONDING
- Patent Title (中): 用于芯片堆叠，芯片和波形结合的方法和材料
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Application No.: PCT/US2007/007029Application Date: 2007-03-21
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Publication No.: WO2007109326A2Publication Date: 2007-09-27
- Inventor: APANIUS, Chris , SHICK, Robert, A. , NG, Hendra
- Applicant: PROMERUS LLC , APANIUS, Chris , SHICK, Robert, A. , NG, Hendra
- Applicant Address: 9921 Brecksville Road, Building R, Brecksville, Ohio 44141 US
- Assignee: PROMERUS LLC,APANIUS, Chris,SHICK, Robert, A.,NG, Hendra
- Current Assignee: PROMERUS LLC,APANIUS, Chris,SHICK, Robert, A.,NG, Hendra
- Current Assignee Address: 9921 Brecksville Road, Building R, Brecksville, Ohio 44141 US
- Agency: REZNICK, Paul, M.
- Priority: US60/784,187 20060321
- Main IPC: H01L21/98
- IPC: H01L21/98 ; H01L25/065
Abstract:
Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.
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