Invention Application
WO2008039975A1 EFFECTIVE USE OF A BHT IN PROCESSOR HAVING VARIABLE LENGTH INSTRUCTION SET EXECUTION MODES
审中-公开
BHT在具有可变长度指令集执行模式的处理器中的有效使用
- Patent Title: EFFECTIVE USE OF A BHT IN PROCESSOR HAVING VARIABLE LENGTH INSTRUCTION SET EXECUTION MODES
- Patent Title (中): BHT在具有可变长度指令集执行模式的处理器中的有效使用
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Application No.: PCT/US2007/079864Application Date: 2007-09-28
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Publication No.: WO2008039975A1Publication Date: 2008-04-03
- Inventor: SMITH, Rodney Wayne , STEMPEL, Brian Michael
- Applicant: QUALCOMM Incorporated , SMITH, Rodney Wayne , STEMPEL, Brian Michael
- Applicant Address: International IP Administration 5775 Morehouse Drive San Diego, California 92121 US
- Assignee: QUALCOMM Incorporated,SMITH, Rodney Wayne,STEMPEL, Brian Michael
- Current Assignee: QUALCOMM Incorporated,SMITH, Rodney Wayne,STEMPEL, Brian Michael
- Current Assignee Address: International IP Administration 5775 Morehouse Drive San Diego, California 92121 US
- Agency: BACHAND, Richard A.
- Priority: US11/536,743 20060929
- Main IPC: G06F9/38
- IPC: G06F9/38
Abstract:
In a processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, line and counter index addresses are formed that access every counter in a branch history table (BHT), and reduce the number of index address bits that are multiplexed based on the current instruction set execution mode. In one embodiment, counters within a BHT line are arranged and indexed in such a manner that half of the BHT can be powered down for each access in one instruction set execution mode.
Information query
