A switch state detector for use in a system wherein a plurality of n switches (S1,..., Sn) produces on a single line (22) a number of discrete voltage levels each representative of one particular state of open and closed switches. The switch state detector comprises a plurality of reference voltage sources each of which corresponds to one of the discrete voltage levels and a set of comparators (C1,..., Cm-1) each having a first input connected to the single line (22) and a second input connected to one of the reference voltage sources. The switch state detector further comprises a decoder (24) with inputs receiving the outputs from the comparators (C1,..., Cm-1) and with outputs (28) providing a digital representation of the particular state of each of the switches (S1,..., Sn). There is further provided an encoder comprising a plurality of n switches (S1,..., Sn) and encoding circuitry interconnecting said n switches as well as a method for communicating an information representative of a particular state of a plurality of n open and closed switches on a single line (22).