Invention Application
- Patent Title: WAFER LEVEL STACKED DIE PACKAGING
- Patent Title (中): 晶圆堆叠的死包装
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Application No.: PCT/US2008078778Application Date: 2008-10-03
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Publication No.: WO2009051975A3Publication Date: 2009-09-24
- Inventor: GOIDA THOMAS M
- Applicant: ANALOG DEVICES INC , GOIDA THOMAS M
- Assignee: ANALOG DEVICES INC,GOIDA THOMAS M
- Current Assignee: ANALOG DEVICES INC,GOIDA THOMAS M
- Priority: US87408307 2007-10-17
- Main IPC: H01L25/065
- IPC: H01L25/065
Abstract:
A method of manufacturing semiconductor devices by applying a pattern of adhesive pads on an active surface of a semiconductor wafer, the semiconductor wafer product so made and a stacked die package in which an adhesive wall leaves an air gap atop a bottom die. The wall may be in the form of a ring of adhesive about a central hollow area. The wafer carrying the pattern of adhesive pads on its active surface is singulated into individual dies, each die having an adhesive pad thereon. The bottom die is attached to a base with an adhesive which cures without curing the adhesive pad.
Public/Granted literature
- WO2009051975A8 WAFER LEVEL STACKED DIE PACKAGING Public/Granted day:2009-10-29
Information query
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