Invention Application
WO2009076531A2 SHARED INTERRUPT CONTROLLER FOR A MULTI-THREADED PROCESSOR 审中-公开
用于多线程处理器的共享中断控制器

SHARED INTERRUPT CONTROLLER FOR A MULTI-THREADED PROCESSOR
Abstract:
A multi-threaded processor is disclosed that includes a sequencer adapted to provide instructions associated with one or more threads of a multi-threaded processor. The sequencer includes an interrupt controller adapted to receive one or more interrupts and to selectively allow a first thread of the one or more threads to service at least one interrupt. The interrupt controller includes logic to preclude a second thread of the one or more threads from responding to the at least one interrupt.
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