Invention Application
- Patent Title: CAPACITOR DIE DESIGN FOR SMALL FORM FACTORS
- Patent Title (中): 小型电容器的电容器模具设计
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Application No.: PCT/US2009064987Application Date: 2009-11-18
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Publication No.: WO2010059724A3Publication Date: 2010-09-10
- Inventor: PAN YUANCHENG CHRISTOPHER , SWEENEY FIFIN , PAYNTER CHARLIE , BOWLES KEVIN R , GONZALEZ JASON R
- Applicant: QUALCOMM INC , PAN YUANCHENG CHRISTOPHER , SWEENEY FIFIN , PAYNTER CHARLIE , BOWLES KEVIN R , GONZALEZ JASON R
- Assignee: QUALCOMM INC,PAN YUANCHENG CHRISTOPHER,SWEENEY FIFIN,PAYNTER CHARLIE,BOWLES KEVIN R,GONZALEZ JASON R
- Current Assignee: QUALCOMM INC,PAN YUANCHENG CHRISTOPHER,SWEENEY FIFIN,PAYNTER CHARLIE,BOWLES KEVIN R,GONZALEZ JASON R
- Priority: US11650508 2008-11-20
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/50 ; H01L23/522 ; H01L23/528
Abstract:
A semiconductor package has a capacitor die and a packaging substrate. The capacitor die is coupled to circuitry on a front or back side of a die coupled to the packaging substrate for providing decoupling capacitance. In one example, the capacitor die is coupled to a land side of the packaging substrate in an area depopulated of a packaging array and adjacent to the packaging array. In another example, the capacitor die may be stacked on the die and coupled through wire bonds to circuitry on the die. The capacitor die reduces impedance of the integrated circuit allowing operation at higher frequencies.
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