Invention Application
- Patent Title: RECTIFIER CIRCUIT WITH REDUCED POWER DISSIPATION
- Patent Title (中): 具有降低功耗的整流器电路
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Application No.: PCT/US2009/038611Application Date: 2009-03-27
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Publication No.: WO2010110802A1Publication Date: 2010-09-30
- Inventor: ATLURI, Prassad, R. , WEBB, William, H.
- Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , ATLURI, Prassad, R. , WEBB, William, H.
- Applicant Address: 11445 Compaq Center Drive W. Houston, TX 77070 US
- Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.,ATLURI, Prassad, R.,WEBB, William, H.
- Current Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.,ATLURI, Prassad, R.,WEBB, William, H.
- Current Assignee Address: 11445 Compaq Center Drive W. Houston, TX 77070 US
- Agency: HART, Kevin, Michael et al.
- Main IPC: H02M7/21
- IPC: H02M7/21 ; H02M7/04
Abstract:
A rectifier circuit for use in a power supply to convert ac input power to dc output power to supply a dc load provides for reduced rectifier circuit power dissipation. The power supply includes a first ac source input line, a second ac source input line, a DC power supply line, and a DC power return line. The rectifier circuit includes a first field effect transistor (FET) having its drain coupled to the first ac source input line and its source coupled to the DC power return line, and a second FET having its drain coupled to the second ac source input line and its source coupled to the DC power return line. During an ac cycle, the first FET closes during the positive half cycle and the second FET closes during the negative half cycle.
Information query
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