Invention Application
- Patent Title: MECHANISM FOR DETECTING A NO-PROCESSOR SWAP CONDITION AND MODIFICATION OF HIGH SPEED BUS CALIBRATION DURING BOOT
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Application No.: PCT/US2010/055454Application Date: 2010-11-04
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Publication No.: WO2011084224A3Publication Date: 2011-07-14
- Inventor: NATU, Mahesh, S. , LOVELACE, John, V. , BANGINWAR, Rajesh, P.
- Applicant: INTEL CORPORATION , NATU, Mahesh, S. , LOVELACE, John, V. , BANGINWAR, Rajesh, P.
- Applicant Address: 2200 Mission College Boulevard Santa Clara, CA 95052 US
- Assignee: INTEL CORPORATION,NATU, Mahesh, S.,LOVELACE, John, V.,BANGINWAR, Rajesh, P.
- Current Assignee: INTEL CORPORATION,NATU, Mahesh, S.,LOVELACE, John, V.,BANGINWAR, Rajesh, P.
- Current Assignee Address: 2200 Mission College Boulevard Santa Clara, CA 95052 US
- Agency: VINCENT, Lester, J. et al.
- Priority: US12/643,108 20091221
- Main IPC: G06F13/14
- IPC: G06F13/14 ; G06F13/38 ; G06F9/44
Abstract:
Memory channel training parameters are function of electrical characteristics of memory devices, processor(s) and memory channel(s). Training steps can be skipped if the BIOS can determine that the memory devices, motherboard and processor have not changed since the last boot. Memory devices contain a serial number for tracking purposes and most motherboards contain a serial number. Many processors do not provide a mechanism by which the BIOS can track the processor. Described herein are techniques that allow the BIOS to track a processor and detect a swap without violating privacy/security requirements.
Information query
