Invention Application
WO2011087589A3 SYSTEM, METHOD, AND APPARATUS FOR A CACHE FLUSH OF A RANGE OF PAGES AND TLB INVALIDATION OF A RANGE OF ENTRIES
审中-公开
系统，方法和装置，用于高速缓存页面和TLB无效的入口范围
- Patent Title: SYSTEM, METHOD, AND APPARATUS FOR A CACHE FLUSH OF A RANGE OF PAGES AND TLB INVALIDATION OF A RANGE OF ENTRIES
- Patent Title (中): 系统，方法和装置，用于高速缓存页面和TLB无效的入口范围
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Application No.: PCT/US2010058236Application Date: 2010-11-29
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Publication No.: WO2011087589A3Publication Date: 2011-10-27
- Inventor: DIXON MARTIN G , RODGERS SCOTT D
- Applicant: INTEL CORP , DIXON MARTIN G , RODGERS SCOTT D
- Assignee: INTEL CORP,DIXON MARTIN G,RODGERS SCOTT D
- Current Assignee: INTEL CORP,DIXON MARTIN G,RODGERS SCOTT D
- Priority: US64454709 2009-12-22
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F9/312
Abstract:
Systems, methods, and apparatus for performing the flushing of a plurality of cache lines and/or the invalidation of a plurality of translation look-aside buffer (TLB) entries is described. In one such method, for flushing a plurality of cache lines of a processor a single instruction including a first field that indicates that the plurality of cache lines of the processor are to be flushed and in response to the single instruction, flushing the plurality of cache lines of the processor.
Information query
