发明申请
WO2011095902A1 PHASE CHANGE MEMORY PROGRAMMING METHOD AND PHASE CHANGE MEMORY
审中-公开
相变存储器编程方法和相位变化记忆
- 专利标题: PHASE CHANGE MEMORY PROGRAMMING METHOD AND PHASE CHANGE MEMORY
- 专利标题(中): 相变存储器编程方法和相位变化记忆
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申请号: PCT/IB2011/050111申请日: 2011-01-11
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公开(公告)号: WO2011095902A1公开(公告)日: 2011-08-11
- 发明人: HURKX, Godefridus, Adrianus , PEREZ GONZALEZ, Jesus
- 申请人: NXP B.V. , HURKX, Godefridus, Adrianus , PEREZ GONZALEZ, Jesus
- 申请人地址: NXP Semiconductors High Tech Campus 60 NL 5656 AG Eindhoven NL
- 专利权人: NXP B.V.,HURKX, Godefridus, Adrianus,PEREZ GONZALEZ, Jesus
- 当前专利权人: NXP B.V.,HURKX, Godefridus, Adrianus,PEREZ GONZALEZ, Jesus
- 当前专利权人地址: NXP Semiconductors High Tech Campus 60 NL 5656 AG Eindhoven NL
- 代理机构: WILLIAMSON, Paul, L et al.
- 优先权: EP10152427.0 20100202
- 主分类号: G11C16/02
- IPC分类号: G11C16/02 ; G11C13/00
摘要:
Disclosed is a method of programming a phase change memory (100) comprising a plurality of memory cells (10), each memory cell comprising a control terminal connected to a word line (30), and a current terminal connected to a bit line (20), comprising applying a first set pulse (Vb) having a shape including a decaying trailing edge (54) to one of the bit line (20) and the word line (30) of a memory cell (10) for changing its phase change material from an amorphous phase to a crystalline phase; applying a second set pulse (Vw) to the other of the bit line and the word line of the memory cell, said second set pulse at least partially overlapping said first set pulse such that the resulting current pulse (Ids) through the memory cell exhibits the decaying trailing edge (52), said decaying trailing edge ensuring the crystallization of the phase change material; applying a first reset pulse (Vb) having said shape to one of the bit line (20) and the word line (30) of a memory cell for changing its phase change material from the crystalline phase to the amorphous phase; and applying a second reset pulse (Vw) to the other of the bit line and the word line of the memory cell, said second set pulse at least partially overlapping said first set pulse such that the resulting current pulse (lds) through the memory cell exhibits the trailing edge of the second reset pulse. A corresponding phase change memory (100) is also disclosed.