Invention Application
WO2011139875A3 TCE COMPENSATION FOR IC PACKAGE SUBSTRATES FOR REDUCED DIE WARPAGE ASSEMBLY
审中-公开
用于减少DIE WARPAGE ASSEMBLY的IC封装基板的TCE补偿
- Patent Title: TCE COMPENSATION FOR IC PACKAGE SUBSTRATES FOR REDUCED DIE WARPAGE ASSEMBLY
- Patent Title (中): 用于减少DIE WARPAGE ASSEMBLY的IC封装基板的TCE补偿
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Application No.: PCT/US2011034444Application Date: 2011-04-29
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Publication No.: WO2011139875A3Publication Date: 2012-02-23
- Inventor: SIMMONS-MATTHEWS MARGARET ROSE
- Applicant: TEXAS INSTRUMENTS INC , TEXAS INSTRUMENTS JAPAN , SIMMONS-MATTHEWS MARGARET ROSE
- Assignee: TEXAS INSTRUMENTS INC,TEXAS INSTRUMENTS JAPAN,SIMMONS-MATTHEWS MARGARET ROSE
- Current Assignee: TEXAS INSTRUMENTS INC,TEXAS INSTRUMENTS JAPAN,SIMMONS-MATTHEWS MARGARET ROSE
- Priority: US77005810 2010-04-29
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/34
Abstract:
A method (100) for assembling die packages includes attaching contacts (101) on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the coefficient of thermal expansion (CTE) mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed (103) from the package substrate. Electrically conductive connectors are attached (104) to the bottom surface of the package substrate, and the package substrate is sawed (105) to form a plurality of singulated die packages.
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