Invention Application
WO2011140552A3 METHOD FOR ATTACHING WIDE BUS MEMORY AND SERIAL MEMORY TO A PROCESSOR WITHIN A CHIP SCALE PACKAGE FOOTPRINT
审中-公开
将总线存储器和串行存储器连接到芯片尺寸封装中的处理器的方法FOOTPRINT
- Patent Title: METHOD FOR ATTACHING WIDE BUS MEMORY AND SERIAL MEMORY TO A PROCESSOR WITHIN A CHIP SCALE PACKAGE FOOTPRINT
- Patent Title (中): 将总线存储器和串行存储器连接到芯片尺寸封装中的处理器的方法FOOTPRINT
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Application No.: PCT/US2011035753Application Date: 2011-05-09
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Publication No.: WO2011140552A3Publication Date: 2012-03-01
- Inventor: WACHTLER KURT , SIMMONS-MATTHEWS MARGARET ROSE
- Applicant: TEXAS INSTRUMENTS INC , TEXAS INSTRUMENTS JAPAN , WACHTLER KURT , SIMMONS-MATTHEWS MARGARET ROSE
- Assignee: TEXAS INSTRUMENTS INC,TEXAS INSTRUMENTS JAPAN,WACHTLER KURT,SIMMONS-MATTHEWS MARGARET ROSE
- Current Assignee: TEXAS INSTRUMENTS INC,TEXAS INSTRUMENTS JAPAN,WACHTLER KURT,SIMMONS-MATTHEWS MARGARET ROSE
- Priority: US77630210 2010-05-07
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/12
Abstract:
A semiconductor device (10) includes a first memory die (12) having a first memory type, a second memory die (14) having a second memory type different from the first memory type, and a logic die (16) such as a microprocessor. The first memory die (12) can be electrically connected to the logic die (16) using a first type of electrical connection preferred for the first memory type. The second memory die (14) can be electrically connected to the logic die using a second type of electrical connection different from the first type of electrical connection which is preferred for the second memory type. Other devices can include dies of the same type, or two or more dies of a first type and two or more dies of a second type different from the first type.
Information query
IPC分类:
