Invention Application
WO2011146823A3 METHOD AND APPARATUS FOR USING CACHE MEMORY IN A SYSTEM THAT SUPPORTS A LOW POWER STATE
审中-公开
在支持低功耗状态的系统中使用高速缓存存储器的方法和装置
- Patent Title: METHOD AND APPARATUS FOR USING CACHE MEMORY IN A SYSTEM THAT SUPPORTS A LOW POWER STATE
- Patent Title (中): 在支持低功耗状态的系统中使用高速缓存存储器的方法和装置
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Application No.: PCT/US2011037319Application Date: 2011-05-20
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Publication No.: WO2011146823A3Publication Date: 2012-04-05
- Inventor: WILKERSON CHRISTOPHER B , WU WEI , ALAMELDEEN ALAA R , LU SHIH-LIEN , CHISHTI ZESHAN A , SOMASEKHAR DINESH
- Applicant: INTEL CORP , WILKERSON CHRISTOPHER B , WU WEI , ALAMELDEEN ALAA R , LU SHIH-LIEN , CHISHTI ZESHAN A , SOMASEKHAR DINESH
- Assignee: INTEL CORP,WILKERSON CHRISTOPHER B,WU WEI,ALAMELDEEN ALAA R,LU SHIH-LIEN,CHISHTI ZESHAN A,SOMASEKHAR DINESH
- Current Assignee: INTEL CORP,WILKERSON CHRISTOPHER B,WU WEI,ALAMELDEEN ALAA R,LU SHIH-LIEN,CHISHTI ZESHAN A,SOMASEKHAR DINESH
- Priority: US78518210 2010-05-21
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F1/32 ; G06F11/10
Abstract:
A cache memory system is provided that uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state.
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