Invention Application
- Patent Title: EFFICIENT AND SCALABLE CYCLIC REDUNDANCY CHECK CIRCUIT USING GALOIS-FIELD ARITHMETIC
-
Application No.: PCT/US2012/044735Application Date: 2012-06-28
-
Publication No.: WO2013006388A3Publication Date: 2013-01-10
- Inventor: RADHAKRISHNAN, Sivakumar , SCHMISSEUR, Mark A. , TAN, Sin S. , HAREN, Kenneth C. , BROWN, Thomas C. , KUMAR, Pankaj , GOPAL, Vinodh , FEGHALI, Wajdi K.
- Applicant: INTEL CORPORATION , RADHAKRISHNAN, Sivakumar , SCHMISSEUR, Mark A. , TAN, Sin S. , HAREN, Kenneth C. , BROWN, Thomas C. , KUMAR, Pankaj , GOPAL, Vinodh , FEGHALI, Wajdi K.
- Applicant Address: 2200 Mission College Boulevard Santa Clara, California 95052 US
- Assignee: INTEL CORPORATION,RADHAKRISHNAN, Sivakumar,SCHMISSEUR, Mark A.,TAN, Sin S.,HAREN, Kenneth C.,BROWN, Thomas C.,KUMAR, Pankaj,GOPAL, Vinodh,FEGHALI, Wajdi K.
- Current Assignee: INTEL CORPORATION,RADHAKRISHNAN, Sivakumar,SCHMISSEUR, Mark A.,TAN, Sin S.,HAREN, Kenneth C.,BROWN, Thomas C.,KUMAR, Pankaj,GOPAL, Vinodh,FEGHALI, Wajdi K.
- Current Assignee Address: 2200 Mission College Boulevard Santa Clara, California 95052 US
- Agency: MAKI, Nathan R.
- Priority: US13/175,500 20110701
- Main IPC: G06F11/10
- IPC: G06F11/10
Abstract:
Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.
Information query
