Invention Application
- Patent Title: POWER EFFICIENT PROCESSOR ARCHITECTURE
- Patent Title (中): 功率有效的处理器架构
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Application No.: PCT/US2011/050580Application Date: 2011-09-06
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Publication No.: WO2013036222A1Publication Date: 2013-03-14
- Inventor: HERDRICH, Andrew, J. , ILLIKKAL, Rameshkumar, G. , IYER, Ravishankar , SRINIVASAN, Sadogopan , MOSES, Jaideep , MAKINENI, Srihari
- Applicant: INTEL CORPORATION , HERDRICH, Andrew, J. , ILLIKKAL, Rameshkumar, G. , IYER, Ravishankar , SRINIVASAN, Sadogopan , MOSES, Jaideep , MAKINENI, Srihari
- Applicant Address: 2200 Mission College Boulevard MS: RNB-4-150 Santa Clara, CA 95052 US
- Assignee: INTEL CORPORATION,HERDRICH, Andrew, J.,ILLIKKAL, Rameshkumar, G.,IYER, Ravishankar,SRINIVASAN, Sadogopan,MOSES, Jaideep,MAKINENI, Srihari
- Current Assignee: INTEL CORPORATION,HERDRICH, Andrew, J.,ILLIKKAL, Rameshkumar, G.,IYER, Ravishankar,SRINIVASAN, Sadogopan,MOSES, Jaideep,MAKINENI, Srihari
- Current Assignee Address: 2200 Mission College Boulevard MS: RNB-4-150 Santa Clara, CA 95052 US
- Agency: TROP, Timothy, N. et al.
- Main IPC: G06F15/80
- IPC: G06F15/80 ; G06F13/24 ; G06F1/32
Abstract:
In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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