Invention Application
WO2013052441A3 STUB MINIMIZATION FOR WIREBOND STACKED ASSEMBLIES WITHOUT WINDOWS
审中-公开
用于无窗口的无线堆叠组件的最小化
- Patent Title: STUB MINIMIZATION FOR WIREBOND STACKED ASSEMBLIES WITHOUT WINDOWS
- Patent Title (中): 用于无窗口的无线堆叠组件的最小化
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Application No.: PCT/US2012058398Application Date: 2012-10-02
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Publication No.: WO2013052441A3Publication Date: 2013-08-15
- Inventor: CRISP RICHARD DEWITT , ZOHNI WAEL , HABA BELGACEM , LAMBRECHT FRANK
- Applicant: INVENSAS CORP
- Assignee: INVENSAS CORP
- Current Assignee: INVENSAS CORP
- Priority: US201161542553 2011-10-03; US201261600271 2012-02-17; US201161542488 2011-10-03
- Main IPC: H01L23/498
- IPC: H01L23/498 ; G11C5/02 ; G11C5/04 ; G11C5/06 ; H01L23/00 ; H01L23/13 ; H01L23/31 ; H01L23/34 ; H01L23/36 ; H01L23/48 ; H01L25/065 ; H01L25/18
Abstract:
A microelectronic package (100) can include a plurality of vertically stacked semiconductor chips 632, 637, the front face of at least one chip facing away from a first substrate surface (108), one or more columns (138, 143) of contacts (132) extending in a first direction (142) along surface (108). Columns (104A, 107B, 109A, 109B) of terminals (105 107) exposed at a second substrate surface (110) extend in the first direction. First terminals (105) disposed in a central region (112) of surface (110) which has width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the at least one semiconductor chip can intersect the central region.
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