Invention Application
- Patent Title: COPPER STUD BUMP WAFER LEVEL PACKAGE
- Patent Title (中): 铜制抛光水平包装
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Application No.: PCT/US2012/052112Application Date: 2012-08-23
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Publication No.: WO2013055453A2Publication Date: 2013-04-18
- Inventor: WARREN, Robert, W. , ROSSI, Nic , LEE, Hyun, Jung
- Applicant: CONEXANT SYSTEMS, INC. , WARREN, Robert, W. , ROSSI, Nic , LEE, Hyun, Jung
- Applicant Address: 4000 MacArthur Boulevard Newport Beach, CA 92660 US
- Assignee: CONEXANT SYSTEMS, INC.,WARREN, Robert, W.,ROSSI, Nic,LEE, Hyun, Jung
- Current Assignee: CONEXANT SYSTEMS, INC.,WARREN, Robert, W.,ROSSI, Nic,LEE, Hyun, Jung
- Current Assignee Address: 4000 MacArthur Boulevard Newport Beach, CA 92660 US
- Agency: FARJAMI, Farshad
- Priority: US13/270,012 20111010
- Main IPC: H01L21/60
- IPC: H01L21/60
Abstract:
There is provided a system and method for a copper stud bump wafer level package. There is provided a semiconductor package comprising a semiconductor die having a plurality of bond pads on an top surface thereof, a plurality of metallic stud bumps mechanically and electrically coupled to said plurality of bond pads, and a plurality of solder balls mechanically and electrically coupled to said plurality of metallic stud bumps. Advantageously, the metallic stud bumps may be provided using standard wirebonding equipment, avoiding the conventional wafer level package requirement for photolithography and deposition steps to provide a multi-layer metallic routing structure. As a result, reduced cycle times, lower cost, and reduced complexity may be provided. Alternative fabrication processes utilizing metallic stud bumps may also support multi-die packages with dies from different wafers and packages with die perimeter pads wirebonded to substrates.
Information query
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