A duty cycle adjustment circuit includes a clock signal input node; a clock signal output node; a control voltage circuit coupled to the clock signal input node; and a first inverter configured to receive an inverter input signal comprising a sum of an input clock signal received at the clock signal input node and a control voltage received from the control voltage generation circuit, and to output an output clock signal at the clock signal at the clock signal output node, wherein variation of the control voltage is configured to vary a duty cycle of the output clock signal.