The invention relates to an electronic circuit (200, 400) comprising a plurality of bit cells (210, 410) arranged in an array and being selectable by row lines (222, 422) and column lines (232, 432), at least one row driver (220, 420), at least one column driver (230, 430), and a readout circuit (260, 460), wherein each bit cell (210, 410) comprises an access transistor (214, 414) and a non-volatile resistive- switching element (212, 412) with at least two resistance states, wherein, in order to write a new data (T_n+1) in a target bit cell (T), said new data depending on a data (S_n) of a source bit cell (S) and on a data (T_n) stored by the target bit cell (T) before sad writing, the row driver (220, 420) and the column driver (230, 430) are capable to simultaneously apply a first selecting voltage (V_s) to a first row line (222, 422) to select the target bit cell (210, 410), a secod selecting voltage (V_p-s) to a second row line (222', 422') to select the source bit cell (210', 410'), and a logic current (l imp) to at least one column line (232, 432), wherein the first selecting voltage (V_s) is higher than the second selecting voltage (V_p-s), such that in response to the voltages applied to the target and source bit cells, the access transistor of the target bit cell ha a lower resistance than the access transistor of the source bit cell.