Invention Application
- Patent Title: HETEROGENEOUS PROCESSOR APPARATUS AND METHOD
- Patent Title (中): 异构处理器装置和方法
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Application No.: PCT/US2013/048352Application Date: 2013-06-27
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Publication No.: WO2014105197A1Publication Date: 2014-07-03
- Inventor: NARVAEZ, Paolo , SRINIVASA, Ganapati, N. , GORBATOV, Eugene , SUBBAREDDY, Dheeraj, R. , NAIK, Mishali , NAVEH, Alon , PRABHAKARAN, Abirami , WEISSMANN, Eliezer , KOUFATY, David, A. , BRETT, Paul , HAHN, Scott, D. , HERDRICH, Andrew, J. , SODHI, Inder, M. , KHANNA, Gaurv , FENGER, Russel, J. , BIGBEE, Bryant, E. , HENROID, Andrew D.
- Applicant: INTEL CORPORATION , NARVAEZ, Paolo , SRINIVASA, Ganapati, N. , GORBATOV, Eugene , SUBBAREDDY, Dheeraj, R. , NAIK, Mishali , NAVEH, Alon , PRABHAKARAN, Abirami , WEISSMANN, Eliezer , KOUFATY, David, A. , BRETT, Paul , HAHN, Scott, D. , HERDRICH, Andrew, J. , SODHI, Inder, M. , KHANNA, Gaurv , FENGER, Russel, J. , BIGBEE, Bryant, E. , HENROID, Andrew D.
- Applicant Address: 2000 Mission College Boulevard M/S: RNB-4-150 Santa Clara, CA 95054 US
- Assignee: INTEL CORPORATION,NARVAEZ, Paolo,SRINIVASA, Ganapati, N.,GORBATOV, Eugene,SUBBAREDDY, Dheeraj, R.,NAIK, Mishali,NAVEH, Alon,PRABHAKARAN, Abirami,WEISSMANN, Eliezer,KOUFATY, David, A.,BRETT, Paul,HAHN, Scott, D.,HERDRICH, Andrew, J.,SODHI, Inder, M.,KHANNA, Gaurv,FENGER, Russel, J.,BIGBEE, Bryant, E.,HENROID, Andrew D.
- Current Assignee: INTEL CORPORATION,NARVAEZ, Paolo,SRINIVASA, Ganapati, N.,GORBATOV, Eugene,SUBBAREDDY, Dheeraj, R.,NAIK, Mishali,NAVEH, Alon,PRABHAKARAN, Abirami,WEISSMANN, Eliezer,KOUFATY, David, A.,BRETT, Paul,HAHN, Scott, D.,HERDRICH, Andrew, J.,SODHI, Inder, M.,KHANNA, Gaurv,FENGER, Russel, J.,BIGBEE, Bryant, E.,HENROID, Andrew D.
- Current Assignee Address: 2000 Mission College Boulevard M/S: RNB-4-150 Santa Clara, CA 95054 US
- Agency: VINCENT, Lester, J. et al.
- Priority: US13/730,565 20121228
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F9/46
Abstract:
A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.
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