A method of generating a target layout of an Integrated circuit Is proposed. The method comprises: providing a source layout comprising one or more source pcells, each source pcell comprising one or more shapes, each shape having a contour composed of edges; providing a set of connectivity constraints for connecting each shape of each source pcell to none, one, or more other components of the integrated circuit: providing a set of target design constraints; for each shape of each source pcell, determining a corresponding target shape, the target shape having a contour composed of edges with defined lengths; for each shape of each source pcell, inserting none, one, or more edges into the contour of the shape, or into the contour of the corresponding target shape, so as to allow for a one-to-one mapping between the edges of the shape of the source pcell and the edges of the corresponding target shape: for each edge of each shape of each source pcell, determining a corresponding edge of the corresponding target shape; for each edge of each shape of each source pcell, defining an edge length constraint for constraining the edge to have the length of the corresponding edge of the corresponding target shape, thus generating a set of edge length constraints; applying a legalization procedure to the source layout on the basis of the set of connectivity constraints, the set of target design constraints, and the set of edge length constraints.