Invention Application
- Patent Title: DEBUGGING DATA PROCESSING TRANSACTIONS
- Patent Title (中): 调查数据处理交易
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Application No.: PCT/GB2015/053559Application Date: 2015-11-23
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Publication No.: WO2016102919A1Publication Date: 2016-06-30
- Inventor: DIESTELHORST, Stephan , WILLIAMS, Michael John , GRISENTHWAITE, Richard Roy , HORSNELL, Matthew James
- Applicant: ARM LIMITED
- Applicant Address: 110 Fulbourn Road Cherry Hinton Cambridge CB1 9NJ GB
- Assignee: ARM LIMITED
- Current Assignee: ARM LIMITED
- Current Assignee Address: 110 Fulbourn Road Cherry Hinton Cambridge CB1 9NJ GB
- Agency: ROBINSON, Nigel
- Priority: GB1423041.1 20141223; GB1423042.9 20141223; GB1500183.7 20150107
- Main IPC: G06F11/36
- IPC: G06F11/36
Abstract:
A data processing system supporting execution of transactions comprising one or more program instructions that execute to generate speculative updates is provided. The speculative updates are committed in normal operation if the transaction completes without a conflict. Start of execution of a transaction may be detected and execution diverted to be performed by software emulation rather than direct execution by the processing hardware. The software emulation may store data representing one or more versions of the speculative updates generated during the emulation. The software emulation may also detect conflicts with the transaction being emulated. In order to facilitate modifying the behaviour of other parts of the system interacting with a transaction under investigation, a non-standard response signal may be returned in response to a detected memory access request to a transaction being emulated. The non-standard response signal may be used to initiate the request source to follow a subsequent path of processing different from that which it would otherwise follow. Support is also provided for detecting a trigger condition which results in the halting (freezing) of a partially completed transaction and the saving the speculative updates associated with that partially completed transaction to the architectural state of the system.
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