Invention Application
- Patent Title: METAL-INSULATOR-METAL (MIM) CAPACITORS ARRANGED IN A PATTERN TO REDUCE INDUCTANCE, AND RELATED METHODS
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Application No.: PCT/US2015/067052Application Date: 2015-12-21
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Publication No.: WO2016106197A3Publication Date: 2016-06-30
- Inventor: YUN, Changhan, Hobie , LAN, Je-Hsiung, Jeffrey , KIM, Daeik, Daniel , BERDY, David, Francis , ZUO, Chengjie , KIM, Jonghae , MUDAKATTE, Niranjan, Sunil , VELEZ, Mario, Francisco , MIKULKA, Robert, Paul
- Applicant: QUALCOMM INCORPORATED
- Applicant Address: ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714 US
- Assignee: QUALCOMM INCORPORATED
- Current Assignee: QUALCOMM INCORPORATED
- Current Assignee Address: ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714 US
- Agency: TERRANOVA, Steven, N.
- Priority: US14/580,900 20141223
- Main IPC: H01L27/08
- IPC: H01L27/08 ; H01L49/02
Abstract:
Metal-insulator-metal (MIM) capacitors arranged in a pattern to reduce inductance, and related methods, are disclosed. In one aspect, circuits are provided that employ MIM capacitors coupled in series. The MIM capacitors are arranged in a pattern, wherein a MIM capacitor is placed so as to be electromagnetically adjacent to at least two MIM capacitors, and so that a current of the MIM capacitor flows in a direction opposite or substantially opposite of a direction in which a current of each adjacent MIM capacitor flows. The magnetic field generated at metal connections of each MIM capacitor rotates in an opposite direction of the magnetic field of each electromagnetically adjacent MIM capacitor, and thus a larger proportion of magnetic fields cancel out one another rather than combining, reducing equivalent series inductance (ESL) compared to linear arrangement of MIMs.
Information query
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