Invention Application
- Patent Title: HIGH VOLTAGE ARCHITECTURE FOR NON-VOLATILE MEMORY
- Patent Title (中): 用于非易失性存储器的高电压结构
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Application No.: PCT/US2016/014581Application Date: 2016-01-22
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Publication No.: WO2016204819A1Publication Date: 2016-12-22
- Inventor: GEORGESCU, Bogdan , MOSCALUK, Gary , RAGHAVAN, Vijay , KOUZNETSOV, Igor
- Applicant: CYPRESS SEMICONDUCTOR CORPORATION
- Applicant Address: 198 Champion Court San Jose, California 95134 US
- Assignee: CYPRESS SEMICONDUCTOR CORPORATION
- Current Assignee: CYPRESS SEMICONDUCTOR CORPORATION
- Current Assignee Address: 198 Champion Court San Jose, California 95134 US
- Priority: US62/175,917 20150615; US14/858,886 20150918
- Main IPC: H01L29/80
- IPC: H01L29/80 ; H01L31/113
Abstract:
A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).
Information query
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