Invention Application
- Patent Title: PACKAGE STACKING USING CHIP TO WAFER BONDING
- Patent Title (中): 堆叠堆叠使用芯片进行晶圆绑定
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Application No.: PCT/US2015/000394Application Date: 2015-12-26
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Publication No.: WO2017111836A1Publication Date: 2017-06-29
- Inventor: SEIDEMANN, Georg , REINGRUBER, Klaus , GEISSLER, Christian , ALBERS, Sven , WOLTER, Andreas , DITTES, Marc , PATTEN, Richard
- Applicant: INTEL IP CORPORATION
- Applicant Address: 2200 Mission College Boulevard Santa Clara, CA 95054 US
- Assignee: INTEL IP CORPORATION
- Current Assignee: INTEL IP CORPORATION
- Current Assignee Address: 2200 Mission College Boulevard Santa Clara, CA 95054 US
- Agency: VAN NESS, Mark, C. et al.
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/48
Abstract:
Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.
Information query
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